
Chapter 1 Introduction Installation and Operation Manual
1-4 Functional Description ASM-40 Ver. 1.0
Timing Generator
This circuit is a PLL circuit. ASM-40 transmits data to the line at the following
baud rates: 2048, 1544, 1536, or 1920 kbps. The baud rates support different
data rates, which enable ASM-40 to be used as a rate converter.
• 2048 kbps – 32, 64, 128, 256, 512, 1024 and 2048 kbps
• 1536 kbps – 192, 384, 768 and 1536 kbps
• 1544 kbps – 1544 kbps
• 1920 kbps – 1920 kbps.
Transmit and receive timing are derived from the following sources:
• Internal – Supplied by the internal crystal oscillator
• External – Supplied by the DTE
• Receive – Recovered from receive signal.
If the DTE interface is a G.703-HDB3 interface, then the recovered clock from this
interface is used as the external clock.
Figure 1-5
shows the ASM-40 clock diagram.
XMT
FIFO
RCV
FIFO
TX
RX
InternalExternal
Receive
TD
RC
RD
TC
EXT CLK
Clock and Data
Clock and Data
Figure 1-5. ASM-40 Clock Diagram
Figure 1-6
shows the clock configuration for ASM-40.
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